Speedway Technology · Atlas
Atlas Librarian is Speedway's segmented cognitive-memory engine.
Atlas Librarian provides the front-door memory authority for Atlas Lattice. Instead of treating memory as one undifferentiated vector of old text, the architecture classifies and routes knowledge into specialized cognitive segments, recalls only the subset relevant to the current task, tracks freshness and lifecycle state, and preserves project continuity across sessions and operational handovers.
The core idea
Memory should be routed by cognitive purpose, not merely stored because it existed.
A long-running operational system accumulates facts, decisions, procedures, incidents, identities, routes, schemas, preferences, deadlines and complete artefacts. Those things do not have the same meaning or lifecycle. Atlas Librarian gives each class an explicit role and lets the memory front door decide which segment should participate in a given recall.
A durable project fact belongs in Semantic Memory; a specific observed outcome belongs in Episodic or Event Memory. Keeping that distinction reduces the risk of treating one historical occurrence as a current truth.
Decision Memory preserves what was chosen and why. Rules Memory represents hard constraints and non-negotiable behaviour. The distinction matters when systems evolve.
Working Memory stays intentionally small and active. Archive Memory preserves low-heat material for long-tail retrieval without crowding immediate reasoning.
The Scheduler is a distinct temporal execution segment so a future condition, reminder or wake event can be represented differently from passive knowledge.
Scratch Pad is distinct from Working Memory because some reasoning depends on complete files, documents, images or structured objects rather than isolated excerpts.
Relationship Memory preserves links among entities, dependencies, causes and supersession chains so recall can expand through meaningful connections.
High-level cognitive flow
Observe, classify, route, retain, selectively recall and continue.
The public architecture can be understood as a governed sequence. The implementation deliberately separates fast active state from durable canonical memory, then promotes material into longer-lived segments when it warrants retention.
An event, handover, project fact, procedure, decision, artefact or other memory candidate reaches the Librarian boundary with provenance and scope.
The current implementation applies deterministic segment-aware classification and normalization. Explicit type and routing information can take precedence when the caller already knows the correct cognitive role.
Short-lived working context can remain in hot state, while durable knowledge is retained in the canonical memory layer with authority, freshness and lifecycle metadata.
Recall begins by identifying the relevant segment and memory candidates rather than treating the full project history as one prompt-sized block.
The selected subset becomes active reasoning context. The architecture distinguishes memory that was merely retrieved from memory that was actually used.
Important working material can be promoted into durable memory; cooled or superseded material can move toward archive while remaining traceable when explicitly needed.
Atlas Lattice
The Librarian is the memory front door inside a broader Atlas architecture.
Speedway refers to the cognitive memory layer as Atlas Lattice, with the Librarian acting as its Conscious Memory Index. The design goal is not to make memory itself the authority for protected business state. Atlas can remember and reason broadly while canonical Speedway services remain authoritative for orders, inventory, payments, identity, permissions and other deterministic records.
Atlas Librarian governs the meaning and lifecycle of Atlas memory. It can record which memory is authoritative within its memory domain and which items are contextual or historical.
Protected business state continues to resolve through the owning Speedway service, policy and permissions. Memory can explain that state without silently becoming a parallel ledger.
This separation lets Atlas carry durable context across work while respecting the authority boundary described in Atlas AI Operations.
Implemented architecture versus evolution
The public technical record distinguishes what exists from what we are still developing.
As of 5 September 2026, the canonical 17-segment registry, deterministic segment-aware classification, hot-state versus durable-memory separation, freshness metadata, fast-recall path, scheduler linkage and memory usage tracking are concrete parts of the Atlas Librarian architecture. Future adaptive classification, ranking or learning improvements should be treated as development direction unless and until they are documented here as implemented.
Canonical segment roles; memory scopes and lifecycle states; thermal states; deterministic classification; index-oriented recall; hot working state; durable retention; scheduler-aware memory; usage and freshness tracking.
This publication does not claim that every future adaptive ranking, autonomous learning or research concept has already been deployed. Speedway will update the technical record as implementation changes.
Private classifier rules, exact scoring thresholds, internal topology, security controls, storage layouts and implementation recipes are not part of the public technical specification.
Read the architecture
Six documents establish the first public Atlas Librarian technical corpus.
Every canonical segment, grouped by cognitive role.
Index-first retrieval, bounded Working Memory and the distinction between recall and use.
Hot, Warm, Cool, Cold and Frozen lifecycle states and freshness-aware retention.
Scheduler, Event Memory and future relevance as a distinct cognitive concern.
Handover, Decision, Procedural, Rules and Episodic Memory working together across sessions.
How Atlas reasoning remains separated from deterministic operational authority.
Canonical definition